The ongoing move to use tools like VPR however will polish a lot of that off (power/timing/clock constraint synthesis). These are all fixable and you can live without them, but that's for a simple EDA tool on the simplest/cheapest consumer FPGA you can buy, with a limited technology library and hard IP. Despite that, I still find myself reaching for iCEcube2, even if my actual flow is IceStorm. Lattice iCEcube2 in terms of features or functionality (timing analysis reports, power estimation, floorplan and pinout UXs, very standard clock synthesis and constraint options, etc etc.) But it's way better at the things it actually does, admittedly. A working flow is one thing, killing it off is a much harder challenge.Įven for Lattice FPGAs, IceStorm does not match e.g. Or even if you're doing semi-serious work. You'll be simulating a lot anyway.īut, Vivado does a lot of very valuable things in practice that will take a lot of time to really replace properly, if you're doing serious FPGA work for Xilinx systems. Also the devices are relatively expensive comparatively. I hope things improve fast, but for now, I’d advise hobbyists who are getting their toes in the water to use closed sourced tools.įor people starting out, yes you can and should absolutely avoid things like Vivado if possible, because they are otherwise big, inscrutable pains in the ass, and you will hate them. And their newer ones aren’t supported by open source tools yet. Unfortunately, what also doesn’t help is that all those cheaper Lattice FPGAs are woefully outdated.
I just have to guess and hope for the best. There is no easy signaltap or chipscope route.
My current workflow is to always develop using Quartus first, and only when things work perfectly I move it over to ICE40.īut even then I sometimes have an identical mid sized RTL design that works perfectly on my small Altera and Xilinx boards, and it just doesn’t work on my ICE40 board.
It’s not the the open source doesn’t work, it usually does, and the small size of it is really nice, it’s that it doesn’t come close in terms of debugging functionality when things go wrong. I hate to rain on the open source FPGA parade, but I do a lot of hobby FPGA stuff using both closed (Quartus, ISE) and open (yosys, arachne) source, and when I have the choice, I go closed source every time I have the chance.
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